Fast-Page Mode (FPM), Extended-Data Out (EDO), Synchronous Dynamic Random Access Memory (SDRAM), and Synchronous Graphic Random Access Memory (SGRAM) are different types of memory used in various Power Macintosh computers. The table below summarizes the types of memory that work with different Power Macintosh computers. Detailed information follows the table.
| Power Macintosh Model | ||||
| 6100, 7100, 8100 | ||||
| 4400 | VRAM: 5 V DRAM: 3.3 V |
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| 5200, 5300, 6200, 6300 | ||||
| 5400, 6360, some 6400 | ||||
| 5500 & 6500 | ||||
| 6400 (some configurations only) | ||||
| 7200 | ||||
| 7300, 7500, 7600, 8500, 8600, 9500, 9600 | DRAM: +5 V |
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| Power Macintosh G3 | ||||
| Power Macintosh G3 (Blue and White) | ||||
| Power Mac G4 (all models) | ||||
| iMac | ||||
| iMac (Slot Loading), (Summer 2000), (Early 2001), Summer 2001) |
Notes
1. The Macintosh Performa 6400/200 computer that includes an internal Zip drive works with EDO memory. EDO memory will operate as FPM memory on other Power Macintosh 6400 computers.
2. The parenthetical product descriptions (Summer 2000) and (Summer 2001) refer to the summer of the Northern Hemisphere.
Fast Paged Mode Memory
A specific location in a memory chip is identified by the row and the column address. Each time memory is accessed, the memory controller first supplies the chip with the row address and then the column address. After the information obtained from these locations is validated, the column deactivates and gets ready for the next cycle. This introduces a wait state because nothing is happening while the column is deactivating. The processor must wait for the memory to complete the cycle.
The Fast Paged Mode (FPM) chip decreased the time required to read these addresses by allowing the memory controller to select a particular row and then access the corresponding column addresses for that row. This process works under the assumption that the next piece of data needed is in the memory location adjacent to the previous piece. Because the row address is only set up once and only the column address changes, this saves time when reading or writing information to or from memory.
EDO Memory
EDO DRAM is a subset of FPM memory that saves the memory controller even more time by allowing it to begin locating the row and column for the next address, while reading the data at the first address. It is able to do this because EDO memory keeps the output buffer on while preparing for the next read operation. By keeping the buffer on, EDO eliminates wait states. This speeds up data transfer rates since EDO RAM can access data continuously without waiting for addresses to be located. This reduces the time of the read cycles by approximately ten percent. However, during write cycles, the system behaves exactly as an FPM chip would behave.
Although EDO devices improve timing efficiency to main memory by approximately ten percent, it does not necessarily mean programs will execute ten percent faster. The processor often gets instructions and data from cached memory, for example, L1 cache within the PowerPC microprocessor and or L2 cache on the logic board.
SDRAM
The processes performed by a computer are coordinated by an internal clock, but memory access has traditionally used its own fixed timers for reading and writing data. Rather than synchronizing its actions with those of the internal clock, memory access had set times for reading and writing data regardless of the actual time the processes required. This would sometimes result in periods of wait cycles where nothing was happening. Because of this, memory was considered to be asynchronous.
However, Synchronous Dynamic Random Access Memory (SDRAM) eliminates this difference between memory speed and processor speed because SDRAM has a clock synchronized with the computer's central processing clock. Thus, SDRAM uses only the time required to read/write data which increases data transfer rates by eliminating non-productive periods of waiting. The clock coordinates with a computer's central processor's clock so that data can be delivered continuously to the microprocessor. The timing coordination between memory, the microprocessor, and other support chips permits more efficient memory access and eliminates wait states. This results in memory access speeds of up to 20% faster than EDO.
Using SDRAM in Power Macintosh computers
The Power Macintosh 4400/200 series support the use of SDRAM ONLY for video memory. You cannot use SDRAM as the primary memory devices on the logic board. The Power Macintosh 4400 series includes 2 MB of EDO memory for video memory, but it supports up to 4 MB of SDRAM or SGRAM.
The Power Macintosh G3, Power Macintosh G3 (Blue and White), Power Mac G4, and iMac support SDRAM for main memory expansion.
SGRAM
Synchronous Graphics Random Access Memory (SGRAM) functions similarly to SDRAM except that it has added graphics support. Graphics support is provided by adding block write and masked write (or write-per-bit) functionality.
Block write enables the graphics engine to do block transfers of graphical data, such as tiling, and to interpret these larger data packets. Block write is often used in 3-D operations to clear the buffers or to prepare them for new rendering. With the block write function in the graphics memory, the graphics engine is free to do other tasks which increases performance. Masked write simplifies changing selected bits in a block of data. Masked write increases graphics performance with tasks such as color management of the display.
Using SGRAM in Power Macintosh computers
SGRAM is supported in the Power Macintosh 4400, 5500, 6500 series, and Power Macintosh G3. SGRAM is supported in these computers for video memory ONLY; you cannot use SGRAM as the primary memory devices on the logic board.
The Power Macintosh 4400 series includes 2 MB of EDO memory for video memory, but it supports up to 4 MB of SDRAM or SGRAM. The Power Macintosh 5500 and 6500 series computers include 2 MB of SGRAM, which is NOT expandable.